Systems and methods for quantum computation using random compiling

ABSTRACT

Systems and methods for executing a quantum computation comprising a plurality gates on a quantum information processor are provided. An initial quantum-logic gate sequence comprising the plurality of gates is received. Then, for each instance in a plurality of instances, a procedure is performed. In each instance of the procedure a respective modified quantum-logic gate sequence is generated by applying a virtual random gate to a first single-qubit gate in the plurality of gates. The respective modified quantum-logic gate sequence is then executed on the quantum device to obtain a respective outcome. The respective outcome across the plurality of instances of the procedure is averaged to obtain a noise-tailored outcome for the initial quantum-logic gate sequence.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority to U.S. patent application Ser. No. 15/882,300, entitled “Systems and Methods for Quantum Computation Using Random Compiling,” filed Jan. 29, 2018, which claims priority to U.S. patent application Ser. No. 15/357,775, entitled “Randomized Compiling for Quantum Computation,” filed Nov. 21, 2016, which claims priority to U.S. Provisional Application No. 62/258,231, entitled “Randomized Compiling for Quantum Computation,” filed Nov. 20, 2015, each of which is hereby incorporated by reference.

GOVERNMENT SUPPORT

This invention was made with government support under grant W911NF-14-1-0103 awarded by the U.S. Army Research Office. The government has certain rights in the invention.

TECHNICAL FIELD

The present disclosure relates generally to systems and methods for randomized compiling for quantum computation.

BACKGROUND

The rich complexity of quantum states and processes enables powerful new protocols for processing and communicating quantum information, as illustrated, for example, by Shor's factoring algorithm, quantum simulation, algorithms, and others. However, the same rich complexity of quantum processes that makes them useful also allows a large variety of errors to occur. Errors in a quantum computation arise from a variety of sources, including decoherence and imperfect control, where the latter can lead to coherent (unitary) errors. Fault-tolerant quantum computation can be performed in the presence of such errors provided they occur with at most some maximum threshold probability.

SUMMARY

The present disclosure addresses the above-identified shortcomings by providing the disclosed systems and methods for executing a quantum computation comprising a plurality gates on a quantum information processor. An initial quantum-logic gate sequence comprising the plurality of gates is received. In some embodiments, at least one gate in the plurality of gates is a non-Clifford gate. Then, for each instance in a plurality of instances, a procedure is performed. In each instance of the procedure a respective modified quantum-logic gate sequence is generated by applying a virtual random gate to a first single-qubit gate in the plurality of gates. The respective modified quantum-logic gate sequence is then executed on the quantum device to obtain a respective outcome. The respective outcome across the plurality of instances of the procedure is averaged to obtain a noise-tailored outcome for the initial quantum-logic gate sequence.

One particular aspect of the present application provides a system comprising a quantum device comprising a quantum information processor and one or more data processors configured to perform a method. In the method, an initial quantum-logic gate sequence comprising a plurality of gates is received. The initial quantum-logic gate sequence is organized into a temporal series of cycles including a k−1 cycle and a k cycle, where the k−1 cycle temporally precedes the k cycle.

In the method, for each respective instance in a plurality of instances, a procedure is executed. The procedure comprises generating a respective modified quantum-logic gate sequence from the initial quantum-logic gate sequence. The respective modified quantum-logic gate comprises (i) a n−1 corresponding cycle representing the k−1 cycle and (ii) an n corresponding cycle representing the k cycle of the initial quantum-logic gate sequence. Furthermore, the n−1 corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a first virtual random gate to a first gate in the k−1 cycle of the initial quantum-logic gate sequence. The n corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a second virtual random gate to a second gate in the k cycle of the initial quantum-logic gate sequence. The first virtual random gate consists of a first random single qubit gate or a combination of the first random single qubit gate and a first correction gate. The second virtual random gate comprises a combination of (1) a second correction gate that inverts the first random single qubit gate and (2) a second random single qubit gate. In the procedure, the respective modified quantum-logic gate sequence is executed on the quantum device to obtain a respective outcome.

In the method, the respective outcome across the plurality of instances is averaged to obtain a noise-tailored outcome for the initial quantum-logic gate sequence.

In some embodiments, the first cycle includes two or more of the plurality of gates, the second cycle includes two or more of the plurality of gates, and at least one gate in the plurality of gates is a non-Clifford gate.

In some embodiments, the second correction gate inverts the first random single qubit gate upon commutation through a second gate, where the second gate is present in both the n−1 cycle of the respective modified quantum-logic gate sequence and the k−1 cycle of the initial quantum-logic gate sequence. In some such embodiments, the second gate is a two-qubit gate.

In some embodiments, the k−1 cycle includes a plurality of single qubit gates, where each single qubit gate in the plurality of single qubit gates is applied to a different qubit in the quantum information processor during the first cycle.

In some embodiments, the n−1 corresponding cycle includes a plurality of single qubit gates, where each single qubit gate in the plurality of single qubit gates is applied to a different qubit in the quantum information processor during the first corresponding cycle.

In some embodiments, the temporal series of cycles further includes a k+1 cycle, where the k cycle temporally precedes the k+1 cycle. In such embodiments, the respective modified quantum-logic gate sequence further comprises (i) a n+1 corresponding cycle representing the k+1 cycle of the initial quantum-logic gate sequence. Further, the n+1 corresponding cycle of the respective modified quantum-logic gate sequence is formed by applying a third virtual random gate to a third single qubit gate in the k+1 cycle of the initial quantum-logic gate sequence. Moreover, the third virtual random gate comprises a combination of (i) a third correction gate that inverts the second random single qubit gate and (ii) a third random single qubit gate. In some such embodiments, the third correction gate inverts the second random single qubit gate upon commutation through a third gate, where the third gate is present in both the n corresponding cycle of the respective modified quantum-logic gate sequence and the k cycle of the initial quantum-logic gate sequence. In some such embodiments, the third gate is a two-qubit gate.

In some embodiments, the plurality of instances of the procedure is at least 1000 instances.

In some embodiments, the k cycle includes two or more of the plurality of gates, the k−1 cycle includes two or more of the plurality of gates not in the k cycle, the first gate is a first single-qubit gate {right arrow over (C)}_(k) in the k cycle and is replaced by the generating in the respective modified quantum-logic gate sequence with a randomized dressed gate {tilde over (C)}_(k), where {tilde over (C)}_(k)={right arrow over (T)}_(k){right arrow over (C)}_(k){right arrow over (T)}_(k−1) ^(c) and where {right arrow over (T)}_(k)=is a first correction gate that is randomly selected from a twirling set T of gates, {right arrow over (T)}_(k−1) ^(c)=G_(k−1){right arrow over (T)}_(k−1) ^(†)G_(k−1) ^(†),{right arrow over (T)}_(k−1) ^(†)=an inverse of a second correction gate {right arrow over (T)}_(k−1) that is randomly selected from the twirling set T of gates, where {right arrow over (T)}_(k−1) is applied to a second gate {right arrow over (C)}_(k−1) in the k−1 cycle, G_(k−1) is a gate in the k−1 cycle other than {right arrow over (C)}_(k−1) or a product of two or more gates in the k−1 cycle other than {right arrow over (C)}_(k−1), and G_(k−1) ^(†) is the inverse of G_(k−1), the first gate {right arrow over (C)}_(k) in the k cycle and the second gate {right arrow over (C)}_(k−1) in the k−1 cycle are members of a set C, the first correction gate {right arrow over (T)}_(k) and the second correction gate {right arrow over (T)}_(k−1) are members of a set T, and the set T is subset of C^(⊗n). In some such embodiments, the first gate {right arrow over (C)}_(k) in the k cycle is a single-qubit Pauli gate in the set {I, X, Y, Z} or a R=|0

0|+i|1

1|, the second gate {right arrow over (C)}_(k−1) in the k−1 cycle is a single-qubit Pauli gate in the set {I, X, Y, Z} or a R=|0

0|+i|1

1|, G_(k−1) comprises a Hardamard gate H, the π/8 gate √{square root over (R)}, or the two-qubit controlled-Z gate Δ(Z)=|0

0|⊗I+|0

0|⊗Z, and G_(k) comprises a Hardamard gate H, the π/8 gate √{square root over (R)}, or the two-qubit controlled-Z gate Δ(Z)=|0

0|⊗I+|0

0|⊗Z.

In some embodiments, the first gate {right arrow over (C)}_(k) in the k cycle is a gate that does not exhibit gate dependent error when implemented on the quantum information processor, and the second gate {right arrow over (C)}_(k−1) in the k−1 cycle is a gate that does not exhibit gate dependent error when implemented on the quantum information processor.

In some embodiments, the first gate {right arrow over (C)}_(k) in the k cycle is a gate that exhibits gate dependent error when implemented on the quantum information processor, and the second gate {right arrow over (C)}_(k−1) in the k−1 cycle is a gate that exhibits gate dependent error when implemented on the quantum information processor. In some such embodiments, the set T is normalized by the set C such that CTC^(†) ∈ T, where C is a first gate in the set C and C^(†) is the logical inverse of the first gate.

In some embodiments, the randomized dressed gate {tilde over (C)}_(k) is one or more elementary gates directly implemented on the quantum information processor as part of the executing the respective modified quantum-logic gate sequence.

In some embodiments, G_(k−1) is a product of two or more gates in the k−1 cycle other than {right arrow over (C)}_(k−1).

In some embodiments, G_(k−1) comprises a two-qubit gate.

In some embodiments, the first gate in the k−1 cycle of the initial quantum-logic gate sequence is configured to act on one or more qubits of the quantum device.

Another aspect of the present disclosure provides a method comprising, at a computer system comprising one or more data processors and a memory, the memory comprising non-transitory instructions configured to receive an initial quantum-logic gate sequence comprising a plurality of gates. The initial quantum-logic gate sequence is organized into a temporal series of cycles including a k−1 cycle and a k cycle. The k−1 cycle temporally precedes the k cycle. For each respective instance in a plurality of instances, a procedure is executed. In the procedure a respective modified quantum-logic gate sequence is generated from the initial quantum-logic gate sequence. The respective modified quantum-logic gate comprises (i) a n−1 corresponding cycle representing the k−1 cycle and (ii) a n corresponding cycle representing the k cycle of the initial quantum-logic gate sequence. The n−1 corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a first virtual random gate to a first gate in the k−1 cycle of the initial quantum-logic gate sequence. The n corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a second virtual random gate to a second gate in the k cycle of the initial quantum-logic gate sequence. The first virtual random gate consists of a first random single qubit gate or a combination of the first random single qubit gate and a first correction gate. The second virtual random gate comprises a combination of (1) a second correction gate that inverts the first random single qubit gate and (2) a second random single qubit gate. The respective modified quantum-logic gate sequence is executed on a quantum device to obtain a respective outcome. The respective outcome is averaged across the plurality of instances to obtain a noise-tailored outcome for the initial quantum-logic gate sequence.

In some such embodiments, the k cycle includes two or more of the plurality of gates, and the k−1 cycle includes two or more of the plurality of gates not in the k cycle. Further, in some such embodiments, the first gate is a first single-qubit gate {right arrow over (C)}_(k) in the k cycle and replaced by the generating in the respective modified quantum-logic gate sequence with a randomized dressed gate {tilde over (C)}_(k), where {tilde over (C)}_(k)={right arrow over (T)}_(k){right arrow over (C)}_(k){right arrow over (T)}_(k−1) ^(c), and where {right arrow over (T)}_(k) is a first correction gate that is randomly selected from a twirling set T of gates, {right arrow over (T)}_(k−1) ^(c)=G_(k−1){right arrow over (T)}_(k−1) ^(†)G_(k−1) ^(†), and {right arrow over (T)}_(k−1) ^(†)=an inverse of a second correction gate {right arrow over (T)}_(k−1) that is randomly selected from the twirling set T of gates. Further {right arrow over (T)}_(k−1) is applied to a second gate {right arrow over (C)}_(k−1) in the k−1 cycle, G_(k−1) is a gate in the k−1 cycle other than {right arrow over (C)}_(k−1) or a product of two or more gates in the k−1 cycle other than {right arrow over (C)}_(k−1), and G_(k−1) ^(†) is the inverse of G_(k−1). In such embodiments, the first gate {right arrow over (C)}_(k) in the k cycle and the second gate {right arrow over (C)}_(k−1) in the k−1 cycle are members of a set C. The first correction gate {right arrow over (T)}_(k) and the second correction gate {right arrow over (T)}_(k−1) are members of a set T, and the set T is subset of C^(⊗n).

In some embodiments, at least one gate in the plurality of gates is a non-Clifford gate.

Another aspect of the present disclosure provides a non-transitory computer readable storage medium storing one or more programs. The one or more programs comprise instructions, which when executed by a computer system with one or more processors, cause the computer system to receive an initial quantum-logic gate sequence comprising a plurality of gates. The initial quantum-logic gate sequence is organized into a temporal series of cycles including a k−1 cycle and a k cycle. The k−1 cycle temporally precedes the k cycle. For each respective instance in a plurality of instances, a procedure is executed. The procedure comprises generating a respective modified quantum-logic gate sequence from the initial quantum-logic gate sequence. The respective modified quantum-logic gate comprises (i) a n−1 corresponding cycle representing the k−1 cycle and (ii) a n corresponding cycle representing the k cycle of the initial quantum-logic gate sequence. The n−1 corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a first virtual random gate to a first gate in the k−1 cycle of the initial quantum-logic gate sequence. The n corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a second virtual random gate to a second gate in the k cycle of the initial quantum-logic gate sequence. The first virtual random gate consists of a first random single qubit gate or a combination of the first random single qubit gate and a first correction gate. The second virtual random gate comprises a combination of (1) a second correction gate that inverts the first random single qubit gate and (2) a second random single qubit gate. The respective modified quantum-logic gate sequence is executed on a quantum device to obtain a respective outcome. The respective outcome is averaged across the plurality of instances to obtain a noise-tailored outcome for the initial quantum-logic gate sequence.

In some embodiments, the k cycle includes two or more of the plurality of gates, the k−1 cycle includes two or more of the plurality of gates not in the k cycle, the first gate is a first single-qubit gate {right arrow over (C)}_(k) in the k cycle and replaced by the generating in the respective modified quantum-logic gate sequence with a randomized dressed gate {tilde over (C)}_(k). Here, {tilde over (C)}_(k)={right arrow over (T)}_(k){right arrow over (C)}_(k){right arrow over (T)}_(k−1) ^(c) and {right arrow over (T)}_(k) is a first correction gate that is randomly selected from a twirling set T of gates, {right arrow over (T)}_(k−1) ^(c)=G_(k−1){right arrow over (T)}_(k−1) ^(†)G_(k−1) ^(†), and {right arrow over (T)}_(k−1) ^(†)=an inverse of a second correction gate {right arrow over (T)}_(k−1) that is randomly selected from the twirling set T of gates. {right arrow over (T)}_(k−1) is applied to a second gate {right arrow over (C)}_(k−1) in the k−1 cycle, G_(k−1) is a gate in the k−1 cycle other than {right arrow over (C)}_(k−1) or a product of two or more gates in the k−1 cycle other than {right arrow over (C)}_(k−1), and G_(k−1) ^(†) is the inverse of G_(k−1). Moreover, the first gate {right arrow over (C)}_(k) in the k cycle and the second gate {right arrow over (C)}_(k−1) in the k−1 cycle are members of a set C, the first correction gate {right arrow over (T)}_(k) and the second correction gate {right arrow over (T)}_(k−1) are members of a set T, and the set T is subset of C^(⊗n). In some such embodiments, at least one gate in the plurality of gates is a non-Clifford gate.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a schematic diagram showing aspects of an example system that includes a compiler system and a quantum device.

FIG. 2 is a flow chart showing an example quantum computation process.

FIG. 3A shows an example of an initial quantum-logic gate sequence.

FIG. 3B shows an example of a modified quantum-logic gate sequence.

FIG. 3C shows another example of a modified quantum-logic gate sequence 300C.

FIG. 4A shows an example of an initial quantum-logic circuit.

FIG. 4B shows an example of a modified quantum-logic circuit.

FIG. 4C shows another example of a modified quantum-logic circuit.

FIG. 4D shows another example of a modified quantum-logic circuit.

FIG. 4E shows a noise-tailored quantum-logic circuit.

FIG. 5 is a plot showing an upper bound on worst-case errors in simulated executions of an example quantum-logic circuit.

FIG. 6 is a plot showing errors in simulated executions of an example quantum-logic circuit.

FIG. 7 is a plot showing errors in simulated executions of an example quantum-logic circuit.

DETAILED DESCRIPTION

In some aspects of what is described here, randomized compiling techniques can convert (or “tailor”) coherent errors into stochastic errors, leading to a reduction in worst-case errors while keeping the average error rate fixed. Such compiling techniques can be used to reduce coherent errors in quantum information processing devices, and in some instances, to achieve fault-tolerant quantum computation.

Some example randomized compiling techniques can achieve a noise reduction (or noise “tailoring”). In some cases, a general technique can be used, for instance, for universal quantum computation, and a variant technique can be used, for instance, for fault-tolerant quantum computation via stabilizer codes. The compiling techniques may be implemented in a manner that is robust under realistic noise models (e.g., under gate-dependent coherent errors).

In some implementations, instead of compiling a gate sequence for a given quantum algorithm into machine code (e.g., pulse sequences, pulse programs, control sequences, etc.) deterministically in one fixed way, virtual random single-qubit gates are introduced into the compiled code, leading to a set of compiled versions of the code that are algorithmically equivalent. The average over these compiled versions has the net effect of creating an effective error model that is stochastic (not coherent). In some cases, the virtual random gates can be implemented as Pauli gates, dihedral gates or other types of gates.

In some implementations, the set of randomized circuits are precomputed. In some implementations, each randomized version can be computed on the fly, for example, using fast classical electronics that control the quantum computation in progress. For instance, the randomized gate sequence at each clock cycle can be computed from information that is local (in space and time). As an example, the randomized gate sequence at each clock cycle may depend only on the bare gates and randomized versions of those gates in the current clock cycle and one adjacent clock cycle (e.g., the previous clock cycle).

Randomized compiling techniques may, in some implementations, achieve one or more of the following advantages, for example, for universal quantum computing or other applications. In some instances, the resulting stochastic noise has a worst-case error rate that can be orders of magnitude lower than under the pre-tailored version of the noise. In some instances, the resulting stochastic noise is guaranteed to satisfy the conditions required for the highest-threshold proofs of fault-tolerant quantum computation (which are orders of magnitude higher). In some instances, the resulting stochastic noise has a worst-case error rate that can be directly estimated via existing experimental techniques (e.g., randomized benchmarking methods), enabling certification of scalability under reasonable assumptions. In some instances, the resulting tailored noise accumulates only linearly instead of quadratically in the length of the circuit. In some instances, randomized compiling may provide decoupling from the environment (e.g., generalizing randomized dynamical decoupling) and reduce the average computational error.

The randomized compiling techniques described here may be used in a number of applications and contexts. For example, in quantum information processing applications, such as quantum simulation and the use of small quantum information processors for repeaters and sensors, tailored (stochastic) noise can evade worst-case scenarios for cumulative noise over a circuit due to the accumulation of coherent errors, and may achieve one or more of the other advantages identified in the preceding paragraph. In some cases, to implement the randomized compiling techniques described here on a quantum device, the experimental overhead cost is relatively small (the gate depth remains unchanged) and the technique can be implemented on the fly, for example, via fast classical control with minimal memory requirements (e.g., instead of pre-compiling all the different but equivalent versions of the quantum algorithm in advance).

FIG. 1 is a schematic diagram showing aspects of an example system 100 that includes a compiler system 106, a quantum device 110 and an interface 108. The quantum device 110 includes a quantum information processor 114. The interface 108 provides communication between the compiler system 106 and the quantum device 110. The system 100 may include additional or different features, and the components of the system 100 may be configured to operate as discussed with respect to FIG. 1 or in another manner.

The example compiler system 106 has computational resources (e.g., hardware, software, firmware) that are used to produce executable instructions (e.g., machine code) for the quantum device 110. In some implementations, the compiler system 106 can be implemented as a classical computer system, such as, for example, a laptop computer, a desktop computer, a computer workstation, a server, a server cluster, a mainframe, or another type of classical computer system. As shown in FIG. 1, the example compiler system 106 includes a memory 102 and a processor 104. The compiler system 106 may include other components, and may be configured to operate in another manner.

In some instances, the memory 102 of the compiler system 106 stores quantum-logic source code to be executed by the quantum information processor 114. For instance, the quantum-logic source code may be stored as quantum-logic gate sequences, quantum-logic circuits, quantum algorithms or other representations of quantum-logic. In some instances, the processor 104 of the compiler system 106 converts the quantum-logic source code into machine code that can be executed by the quantum information processor 114. For instance, the machine code may be stored as a pulse sequence (e.g., radio frequency, microwave frequency, optical frequency), a pulse program, or another type of control sequence configured for execution by the quantum information processor 114. The machine code can be stored on the memory 102 of the compiler system 106, transferred to the quantum device 110 via the interface 108, or handled in another manner.

The example memory 102 can include, for example, random access memory (RAM), a storage device (e.g., a writable read-only memory (ROM) or others), a hard disk, or another type of storage medium. The example memory 102 can store instructions (e.g., computer code, a computer program, etc.) associated with an operating system, computer applications and other resources. The memory 102 can also store application data and data objects that can be interpreted by one or more applications or virtual machines running on the compiler system 106. In some cases, the memory 102 stores computer-readable instructions for software applications, scripts, programs, functions, executables or other modules that are executed by the processor 104. For example, the computer-readable instructions may be configured to perform one or more of the operations shown in FIG. 2.

The example processor 104 can execute instructions, for example, to generate output data based on data inputs. For example, the processor 104 can run computer programs by executing the software, scripts, programs, functions, executables, or other modules stored in the memory 102. In some instances, the processor 104 may perform one or more of the operations shown in FIG. 2. The example processor 104 shown in FIG. 1 can include one or more chips or chipsets that include analog circuitry, digital circuitry or a combination thereof. In some cases, the processor 104 includes multiple processor devices such as, for example, one or more main processors and one or more co-processors.

In some aspects of operation, the compiler system 106 obtains quantum-logic source code (e.g., a quantum-logic gate sequence, a quantum-logic circuit, a quantum algorithm, etc.), modifies the quantum-logic source code, and provides the modified quantum-logic source code to the quantum device 110 for execution by the quantum information processor 114. For instance, the quantum-logic source code can be modified to reduce the effects of noise in the quantum information processor 114. FIGS. 3A-3C and 4A-4E show examples of how quantum-logic source code can be modified to tailor noise in a quantum information processor. The compiler system 106 may compile portions (e.g., one or more clock cycles) of the quantum-logic source code “on-the-fly” while the quantum information processor 114 executes earlier-compiled portions (e.g., earlier clock cycles). For instance, each cycle of the modified quantum-logic source code may be provided to the quantum device 110 individually. The compiler system 106 may pre-compile the quantum-logic source code before the quantum information processor 114 begins execution. For instance, all cycles of the modified quantum-logic source code may be provided to the quantum device 110 together. The compiler system 106 may operate in another manner.

The example quantum device 110 can be a quantum computer, a quantum sensor, a quantum repeater or another type of device that operates using a quantum information processor. For example, the quantum device 110 may be a universal quantum computer that operates in a fault-tolerant regime and can be programmed and reprogrammed to perform computations. As another example, the quantum device 110 may be a quantum repeater that performs quantum error correction in an optical network used for quantum key distribution scheme. As another example, the quantum device 110 can be a quantum sensor that can measure physical properties of an external system based on quantum interactions or phenomena.

The example quantum information processor 114 can include hardware, software, firmware, or combinations thereof configured to process quantum information. The quantum information processor 114 can be implemented using any suitable computing architecture or physical modality for quantum computing (e.g., trapped ion systems, SQUID-based systems, spin-based systems, optical systems, etc.). The quantum information processor 114 may be programmed, or it may be programmable, to realize a quantum-logic circuit or multiple quantum-logic circuits. For example, the quantum information processor 114 may be programmed to perform one or more the operations shown in FIGS. 3A-3C and 4A-4E. The quantum information processor 114 can be a universal quantum computer, or the quantum information processor 114 can be a quantum computer without universal quantum computation capabilities.

The example quantum information processor 114 can store quantum information in a Hilbert space defined by a quantum system. The quantum information processor 114 can store any suitable number of qubits (i.e., quantum bits), and the Hilbert space can be any suitable size. For example, the quantum information processor 114 can store n qubits in a 2^(n)-dimensional Hilbert space. The quantum information processor 114 can perform quantum computing operations that manipulate the quantum information in the Hilbert space. For example, the quantum information processor 114 may coherently control the quantum system and preserve the relative phases of the qubits. If the quantum information processor 114 is a universal quantum computer, it can generally create any coherent state in the Hilbert space. The quantum information processor 114 can be configured to measure the state of the quantum system in a suitable basis. For example, the quantum information processor 114 may be configured to measure one or more of the qubits in a computational basis.

The quantum information processor 114 may be subject to noise that can create errors. The noise can include, for example, coherent noise processes, incoherent noise processes, or decoherent noise processes. In some cases, the quantum information processor 114 can perform a quantum error correction process that effectively counteracts the noise. In some cases, the compiler system 106 can modify quantum-logic source code to tailor the noise affecting the quantum information processor 114. For example, the compiler system 106 can convert an arbitrary noise process into stochastic Pauli noise in some instances.

The example interface 108 can include all or part of a connector, a data communication network or another type of communication link. For example, the interface 108 can include one or more wired or wireless connections, one or more wired or wireless networks or other communication channels. In some examples, the interface 108 includes a Local Area Network (LAN), a Wide Area Network (WAN), a private network, a Virtual Private Network (VPN), a public network (such as the Internet), a peer-to-peer network, a cellular network, a Wi-Fi network, a Personal Area Network (PAN) or another type of data communication network. In some examples, the interface 108 includes a wired communication interface (e.g., USB, Ethernet, coaxial, optical) that can be connected directly or indirectly between the compiler system 106 and the quantum device 110.

FIG. 2 is a flow chart showing an example quantum. computation process 200. The example process 200 can be performed, for example, by a computer system, by the example system 100 shown in FIG. 1 or by another type of system. In some cases, one or more of the operations shown in FIG. 2 are implemented as processes that include multiple operations, sub-processes or other types of routines. In some cases, operations can be combined, performed in parallel, iterated or otherwise repeated or performed in another manner.

At 202, an initial gate sequence is received. As an example, the initial gate sequence can be received by a compiler system (e.g., the compiler system 106 shown in FIG. 1 or another compiler system). The initial gate sequence is an initial quantum-logic gate sequence representing quantum-logic to be executed by a quantum information processor (e.g., by the quantum information processor 114 shown in FIG. 1 or another type of quantum information processor). For example, the initial quantum-logic gate sequence can be in the form of quantum-logic source code, or the initial quantum-logic gate sequence can be in another form or format. The initial gate sequence can be received from memory, from an external system, from a processor or another source.

In some implementations, the initial quantum-logic gate sequence includes a series of cycles (e.g., clock cycles or other types of cycles). Each cycle can include a set of single-qubit gates (i.e., quantum-logic operations applied to individual qubits) and a set of multi-qubit gates (i.e., quantum-logic operations applied to multiple qubits). An example of an initial quantum-logic gate sequence that includes a series of cycles is shown in FIG. 3A.

At 204, virtual random gates are applied to the initial gate sequence. The virtual random gates can be applied by a data processing apparatus of the compiler system (e.g., by operation of the processor 104 shown in FIG. 1 or another type of processor). A modified quantum-logic gate sequence is generated by applying virtual random gates to the initial quantum-logic gate sequence. For instance, random gates can be effectively inserted in the initial quantum-logic gate sequence and combined with the quantum-logic gates to form a new, modified quantum-logic gate sequence. In some cases, all of the virtual random gates are single-qubit quantum-logic operations. For instance, the virtual random gates can be virtual random Pauli gates or dihedral gates. Virtual random Pauli gates are virtual gates randomly selected from the standard set of single-qubit Pauli gates {X, Y, Z}. Virtual random dihedral gates are virtual gates compiled from a randomly selected element of the standard set of single-qubit Pauli gates and a random power of the standard single-qubit phase gate.

In some implementations, the virtual random gates are configured to reduce the effect of noise in the quantum information processor. For example, the virtual random gates can be configured to convert coherent errors in the quantum information processor into stochastic errors in the quantum information processor. Coherent errors are created by coherent noise processes, such as, for example, noise processes that produce unitary operations in the Hilbert space of the quantum information processor. Stochastic errors are created by stochastic noise processes, such as, for example, randomly-applied Pauli operations. Stochastic noise processes lack coherence, and are generally statistical in nature. In some instances, stochastic errors can be tolerated more easily than coherent errors in a quantum information processor. Accordingly, applying the virtual random gates may improve performance of the quantum information processor, for instance, by reducing or modifying errors.

The virtual random gates can be applied in a manner that ensures the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence. For instance, the virtual random gates can be applied in pairs, such that the first virtual random gate in each pair is inverted by the second virtual random gate in the pair. In cases where the initial quantum-logic gate sequence includes a series of cycles, the modified quantum-logic gate sequence can be generated by applying virtual random gates in each cycle of the initial quantum-logic gate sequence. For instance, after the initial cycle in the series, a portion of the virtual random gates applied in each cycle can be configured to invert one or more of the virtual random gates applied in the preceding cycle. In some cases, a pair of virtual random gates is applied to each qubit in each cycle.

At 206, a modified gate sequence is provided. The modified gate sequence provided at 206 is a modified quantum-logic gate sequence, which is provided to the quantum information processor for execution. Providing the modified quantum-logic gate sequence to be executed by the quantum information processor can include converting the modified quantum-logic gate sequence into machine code (e.g., a pulse program, pulse sequence, control sequence, etc.) that is executable by the quantum information processor. In the example shown in FIG. 1, the compiler system 106 can convert the modified quantum-logic gate sequence from quantum-logic source code to machine code that can be executed by the quantum information processor 114. The machine code can be delivered to the quantum information processor, for instance, by transferring digital information to the quantum information processor. In the example shown in FIG. 1, machine code generated by the compiler system 106 can be delivered to the quantum information processor 114 by communicating the machine code through the interface 108. The machine code may be delivered as computer file, computer code, an electronic document or in another format, and the machine code may be delivered. in any suitable form (e.g., binary, text, or other digital form).

At 208, the modified gate sequence is executed. For example, the quantum information processor may execute the machine code representing the modified quantum-logic gate sequence. In some implementations, the quantum information processor converts the machine code into physical control signals that interact with the qubits and cause the quantum information processor to execute the quantum-logic represented by the modified quantum-logic gate sequence (and equivalently by the initial quantum-logic gate sequence). As an example, when the machine code takes the form of a pulse sequence, the quantum information processor may convert the pulse sequence into pulses (e.g., radio-frequency pulses, microwave pulses, optical pulses, etc.) that manipulate the quantum states of the qubits in the quantum information processor.

As shown in FIG. 2, the operations 204, 206, 208 may be performed in an iterative manner. For instance, each iteration of operations 204, 206, 208 may apply a different set of virtual random gates at 204. In some cases, the set of virtual random gates applied at 204 on each iteration of the process 200 is determined independent of the set of virtual random gates applied at 204 on other iterations. Thus, a distinct modified quantum-logic gate sequence may be provided at 206 upon each iteration of the process 200, and each distinct modified quantum-logic gate sequence may be logically equivalent to the initial quantum-logic gate sequence received at 202. A different set of errors may be produced by executing each distinct modified quantum-logic gate sequence at 208. For instance, the noise affecting the quantum information processor may be gate-dependent, temporally-dependent, state-dependent or otherwise vary under the distinct properties of each modified quantum-logic gate sequence.

The process 200 may be iterated, for example, for a specified number of iterations, for a specified duration of time, or until another condition is met, and the outcomes from multiple executions can be averaged or combined. In some implementations, averaging over multiple executions of the process (and therefore averaging over the errors produced by multiple distinct modified quantum-logic gate sequences) can reduce the overall or statistical effects of noise in the quantum information processor.

FIGS. 3A, 3B, and 3C are schematic diagrams showing an example of noise tailoring applied to a quantum-logic gate sequence. FIG. 3A shows an example of an initial quantum-logic gate sequence 300A. FIG. 3B shows an example of a modified quantum-logic gate sequence 300B, which is the initial quantum-logic gate sequence 300A of FIG. 3A with virtual random gates 308 inserted. FIG. 3C shows another example of a modified quantum-logic gate sequence 300C, which is the initial quantum-logic gate sequence 300A of FIG. 3A transformed by application of the virtual random gates 308 shown in FIG. 3B.

The example initial quantum-logic gate sequence 300A shown in FIG. 3A includes three-and-a-half cycles of quantum-logic gates applied to four qubits. Each cycle includes a single-qubit gate applied to each qubit, and a two-qubit gate 304 applied to a pair of the qubits. For example, in the first full cycle, a single-qubit gate 302A is applied to the first qubit, a single-qubit gate 302B is applied to the second qubit, a single-qubit gate 302C is applied to the third qubit, a single-qubit gate 302D is applied to the third qubit, and then a two-qubit gate 304A (a controlled-not gate, in this example) is applied to the second and third qubits. The single-qubit gates and the two-qubit gates in FIG. 3A are collectively referred to as “single-qubit gates 302” and “two-qubit gates 304,” respectively. Generally, each of the single-qubit gates 302 in the initial quantum-logic gate sequence 300A may be different from the others, and each of the two-qubit gates 304 in the initial quantum-logic gate sequence 300A may be different from the others.

The example modified quantum-logic gate sequence 3008 shown in FIG. 3B includes virtual random gates 308 inserted into the initial quantum-logic gate sequence 300A. For example, in the first cycle, a single-qubit virtual random gate 308A is applied to the first qubit, a single-qubit virtual random gate 308B is applied to the second qubit, a single-qubit virtual random gate 308C is applied to the third qubit, a single-qubit virtual random gate 308D is applied to the fourth qubit. The virtual random gates in FIG. 3B are collectively referred to as “virtual random gates 308.” The attributes of each virtual random gate can be determined by a random process, for example, independent of the initial quantum-logic gate sequence 300A.

In the example shown in FIG. 3B, the virtual random gates 308 are applied in pairs, one before the two-qubit gate of each cycle and the other after the two-qubit gate of the cycle. The second virtual random gate in each pair inverts the first virtual random gate in the pair when commuted through the two-qubit gate. As an example, the virtual random gates 308E, 308H applied to the first and fourth qubits are the inverse of (i.e., they invert) the virtual random gates 308A, 308D), respectively. Similarly, the virtual random gates 308F, 308G applied to the second and third qubits are the inverse of (i.e., they invert) the virtual random gates 308B, 308C, respectively, when commuted through the two-qubit gate 304A. Because each of the virtual random gates 308 is inverted, the modified quantum-logic gate sequence 3008 shown in FIG. 3B is logically equivalent to the initial quantum-logic gate sequence 300A shown in FIG. 3A.

The example modified quantum-logic gate sequence 300C shown in FIG. 3C is the modified quantum-logic gate sequence 300B of FIG. 3B, where the virtual random gates 308 have been combined with the adjacent single-qubit gates 302. For example, the modified single-qubit gate 310A is logically equivalent to the single-qubit gate 302A (from the initial quantum-logic gate sequence 300A) followed by the virtual random gate 308A. Similarly, the modified single-qubit gate 310F is logically equivalent to the virtual random gate 308F followed by the single-qubit gate 302F (from the initial quantum-logic gate sequence 300A) followed by the virtual random gate 308J.

Accordingly, the modified quantum-logic gate sequence 300C shown in FIG. 3C is logically equivalent to the modified quantum-logic gate sequence 300B shown in FIG. 3B and the initial quantum-logic gate sequence 300A shown in FIG. 3A. Thus, the modified quantum-logic gate sequence 300C shown in FIG. 3C represents the initial quantum-logic gate sequence 300A shown in FIG. 3A transformed by application of the virtual random gates 308 shown in FIG. 3B. Like the initial quantum-logic gate sequence 300A shown in FIG. 3A, each cycle in the modified quantum-logic gate sequence 300C includes a single-qubit gate applied to each qubit, and a two-qubit gate 304 applied to a pair of the qubits.

FIGS. 4A, 4B, 4C, 4D and 4E are schematic diagrams showing an example of noise tailoring applied to a quantum-logic circuit. FIG. 4A shows an example of a bare quantum-logic circuit 400A. FIG. 4B shows an example of a modified quantum-logic circuit 400B, which is the bare quantum-logic circuit 400A of FIG. 4A with twirling gates 412 and correction gates 413 inserted. FIG. 4C shows an example of a modified quantum-logic circuit 400C, which is the modified quantum-logic circuit 400B of FIG. 48 with the correction gates 413 repositioned. FIG. 4D shows an example of a modified quantum-logic circuit 400D, which is the modified quantum-logic circuit 400C of FIG. 4C with the twirling gates 412 and correction gates 413 combined with adjacent single-qubit gates 404. FIG. 4E shows an example of a noise-tailored quantum-logic circuit 400E, which is the modified quantum-logic circuit 400D of FIG. 4D averaged over multiple realizations.

The bare quantum-logic circuit 400A shown in FIG. 4A includes the k-th cycle 402A of quantum-logic gates and part of a subsequent (k+1)-th cycle of quantum-logic gates. Each cycle includes an “easy” single-qubit gate 404 applied to each qubit, and a set of one or more “hard” gates 410 applied to one or more qubits. In particular, the k-th cycle 402A includes a single-qubit gate 404A applied to the first qubit, a single-qubit gate 404B applied to the second qubit and a single-qubit gate 404C applied to the third qubit; and the one or more gates 410 may generally include one or more multi-qubit gates applied to respective pairs of the qubits. In some cases, one or more of the “easy” or “hard” gates can be an identity operation (and may therefore be omitted) in one or more cycles of the bare quantum-logic circuit 400A. The single-qubit gates in FIG. 4A are collectively referred to as “single-qubit gates 404.”

Noise affecting an execution of the bare quantum-logic circuit 400A by a quantum information processor is also represented in FIG. 4A. In particular, the noise affecting an execution of the k-th cycle 402A is represented as a fixed noise channel 406 and a gate-dependent noise channel 408. The fixed noise channel 406 does not depend on the particular gates executed by the quantum information processor, while the gate-dependent noise channel 408 does depend on the particular gates executed by the quantum information processor.

The modified quantum-logic circuit 400B shown in FIG. 4B includes a k-th cycle 402B that has been modified by the insertion of twirling gates 412 and correction gates 413 into the k-th cycle 402A of the bare quantum-logic circuit 400A. In particular, the k-th cycle 402B includes a twirling gate 412A and a corresponding correction gate 413A applied to the first qubit, a twirling gate 412B and a corresponding correction gate 413B applied to the second qubit and a twirling gate 412C and a corresponding correction gate 413C applied to the third qubit. The twirling gates and the correction gates in FIG. 4B are collectively referred to as “twirling gates 412” and “correction gates 413,” respectively.

The attributes of each twirling gate 412 can be determined by a random process, for example, independent of the bare quantum-logic circuit 400A. The correction gate 413 applied to each qubit is the logical inverse of the twirling gate 412 applied to the qubit. As an example, the correction gate 413A is the inverse of the twirling gate 412A. Because each of the twirling gates 412 is inverted, the modified quantum-logic circuit 400B shown in FIG. 4B is logically equivalent to the bare quantum-logic circuit 400A shown in FIG. 4A.

The modified quantum-logic circuit. 400C shown in FIG. 4C includes a k-th cycle 402C that has been modified by the removing the correction gates 413A, 413B, 413C from the k-th cycle 402B of the modified quantum-logic circuit 400B. In FIG. 4C, the correction gates 413A, 413B, 413C have been commuted through the “hard” gates 410 to form modified correction gates 413D, 413E, 413F, respectively, and the modified correction gates 413D, 413E, 413F have been associated with the (k+1)-th cycle of the quantum-logic circuit. By commuting the initial correction gates 413A, 413B, 413C through the “hard” gates 410, the initial correction gates 413A, 413B, 413C are transformed to define the modified correction gates 413D, 413E, 413F, such that the “hard” gates 410 followed by the modified correction gates 413D, 413E, 413F is logically equivalent to the initial correction gates 413A, 413B, 413C followed by the “hard” gates 410. Accordingly, the modified quantum-logic circuit 400C shown in FIG. 4C is logically equivalent to the modified quantum-logic circuit 400B shown in FIG. 4B and the bare quantum-logic circuit 400A shown in FIG. 4A.

The modified quantum-logic circuit 400D shown in FIG. 4D is the modified quantum-logic circuit 400C of FIG. 4C, where the twirling gates 412 and correction gates 413 have been combined with the adjacent single-qubit gates 404. For example, the modified single-qubit gate 404G is logically equivalent to the single-qubit gate 404A (from the initial quantum-logic gate circuit 400A) followed by the twirling gate 412A. Similarly, the modified single-qubit gate 404J is logically equivalent to the correction gate 413D followed by the single-qubit gate 404D (from the initial quantum-logic gate circuit 400A).

Accordingly, the modified quantum-logic circuit 400D shown in FIG. 4D is logically equivalent to the modified quantum-logic circuit 400C shown in FIG. 4C and the bare quantum-logic circuit 400A shown in FIG. 4A. Thus, the modified quantum-logic circuit 400D shown in FIG. 4D represents the bare quantum-logic circuit 400A shown in FIG. 4A transformed by application of the twirling gates 412 and correction gates 413 shown in FIG. 4B. Like the bare quantum-logic circuit 400A shown in FIG. 4A, each cycle in the modified quantum-logic circuit 400D includes an “easy” single-qubit gate applied to each qubit, and a set of one or more “hard” gates 410 applied to one or more qubits.

The modified quantum-logic circuit 400C in FIG. 4C can be executed by a quantum information processor with the twirling gates 412 and correction gates 413 incorporated as virtual gates, for example with the twirling gates 412 and correction gates 413 applied to the single-qubit gates 404 as shown in FIG. 4D. The virtual twirling gates and virtual correction gates may cause the quantum information processor to execute the modified quantum-logic circuit with a lower worst-case error rate compared to executing the bare quantum-logic circuit 400A on the quantum information processor. The worst-case error rate is the error rate when the quantum-logic circuit is applied to an input state that triggers the worst performance of the quantum-logic circuit. The worst-case error rate may be computed, for example, as in Equation (2), in terms of the diamond norm, or the worst-case error rate may be computed in another manner in some cases. The virtual twirling gates and virtual correction gates may cause the quantum information processor to execute the modified quantum-logic circuit with a lower average error rate compared to executing the bare quantum-logic circuit 400A on the quantum information processor. The average error rate is the average error rate of the quantum-logic circuit applied to a set of input states. The average error rate may be computed, for example, as in Equation (1), in terms of the fidelity averaged over the set of input states, or the average error rate may be computed in another manner in some cases.

In some cases, a set of distinct quantum-logic circuits is executed by a quantum information processor to obtain a set of outcomes. Each of the distinct quantum-logic circuits can be based on the modified quantum-logic circuit 400C in FIG. 4C, with the twirling gates 412 and correction gates 413 randomized and incorporated as virtual twirling gates and virtual correction gates (as in FIG. 4D). The outcome for each of the distinct quantum-logic circuits can include a measurement of the quantum state produced by the quantum-logic circuit. Each of the outcomes may depend on the specific virtual twirling gates applied in associated quantum-logic circuit, and so the outcomes may be different for each distinct quantum-logic circuit. The outcomes can be combined (e.g., averaged) to obtain a noise-tailored outcome for the set of distinct quantum-logic circuits.

The noise-tailored quantum-logic circuit 400E shown in FIG. 4E is the modified quantum-logic circuit 400D of FIG. 4D averaged over multiple realizations of randomly selecting the virtual twirling gates. The fixed noise channel 406 and the gate-dependent noise channel 408 in each cycle are modified by the virtual twirling gates and virtual correction gates, and the modified noise affecting an execution of the k-th cycle 402E is represented as the tailored noise channel 414. The virtual twirling gates can be independently selected for each realization. In some implementations, a sufficient number of realizations can suppress the worst case close to its actual probability, which is typically low. The number of realizations can be chosen to statistically bound the probability that the average outcome obtained is within a certain threshold from the actual average outcome over all possible outcomes.

Quantum computers are poised to radically outperform their classical counterparts by manipulating coherent quantum systems. A realistic quantum computer will experience errors due to the environment and imperfect control. When these errors are even partially coherent, they present a major obstacle to performing robust computations. Here, we propose a method for introducing independent random single-qubit gates into the logical circuit in such a way that the effective logical circuit remains unchanged. We prove that this randomization tailors the noise into stochastic Pauli errors, which can dramatically reduce error rates while introducing little or no experimental overhead. Moreover, we prove that our technique is robust to the inevitable variation in errors over the randomizing gales and numerically illustrate the dramatic reductions in worst-ease error that are achievable. Given such tailored noise, gates with significantly lower fidelity—comparable to fidelities realized in current experiments—are sufficient to achieve fault-tolerant quantum computation. Furthermore, the worst-case error rate of the tailored noise can be directly and efficiently measured through randomized benchmarking protocols, enabling rigorous certification of the performance of a quantum computer.

The rich complexity of quantum states and processes enables powerful new protocols for processing and communicating quantum information, as illustrated by Shor's factoring algorithm and quantum simulation algorithms. However, the same rich complexity of quantum processes that makes them useful also allows a large variety of errors to occur. Errors in a quantum computer arise from a variety of sources, including decoherence and imperfect control, where the latter generally lead to coherent (unitary) errors. It is provably possible to perform a fault-tolerant quantum computation in the presence of such errors provided they occur with at most some maximum threshold probability. However, the fault-tolerant threshold probability depends upon the error-correcting code and is notoriously difficult to estimate or bound because of the sheer variety of possible errors. Rigorous lower bounds on the threshold of the order of 10⁻⁶ for generic local noise and 10⁻⁴ and 10⁻³ for stochastic Pauli noise have been obtained for a variety of codes. While, these bounds are rigorous, they are far below numerical estimates that range from 10⁻² and 10⁻¹, which-are generally obtained-assuming stochastic Pauli noise, largely because the effect of other errors is too difficult to simulate. While a threshold for Pauli errors implies a threshold exists for arbitrary errors (e.g., unitary errors), there is currently no known way to rigorously estimate a threshold for general noise from a threshold for Pauli noise.

The “error rate” due to an arbitrary noise map E can be quantified in a variety of ways. Two particularly important quantities are the average error rate defined via the gate fidelity

r(ε)=1−∫dψ

ψ|ε(|ψ

ψ|)|ψ

  (1)

and the worst-case error rate (also known as the diamond distance from the identity)

ɛ  ( ℰ ) = 1 2   ℰ -  o = sup ψ  1 2   [ ℰ ⊗ d - d 2 ]  ( ψ )  1 ( 2 )

where d is the dimension of the system ε acts on, ∥A∥₁=√{square root over (TrA^(†)A)} and the maximization is over all d²-dimensional pure states (to account for the error introduced when acting on entangled states). The average error rate r(ε) is an experimentally-convenient characterization of the error rate because it can be efficiently estimated via randomized benchmarking. However, the diamond distance is typically the quantity used to prove rigorous fault-tolerance thresholds. The average error rate and the worst-case error rate are related via the bounds

r(ε)d ⁻¹(d+1)≤ε(ε)≤√{square root over (r)}(ε)√{square root over (d(d+1))}.   (3)

The lower bound is saturated by any stochastic Pauli noise, in which case the worst-case error rate is effectively equivalent to the experimental estimates obtained efficiently via randomized benchmarking. While the upper bound is not known to be tight, there exist unitary channels such that ε(ε)≈√{square root over ((d+1)r(ε)/4)}, so the scaling with r is optimal.

The scaling of the upper bound of equation (3) is only saturated by purely unitary noise. However, even a small coherent error relative to stochastic errors can result in a dramatic increase in the worst-case error. For example, consider a single qubit noise channel with r=1×10⁻⁴, where the contribution due to stochastic noise processes is r=0.83×10⁻⁴ and the remaining contribution is from a small unitary (coherent) rotation error. The worst-case error for such noise is ε≈10⁻², essentially two orders of magnitude greater than the infidelity.

Here we show that by compiling random single-gate gates into a logical circuit, noise with arbitrary coherence and spatial correlations can be converted (or “tailored”) into stochastic Pauli noise. We also prove that our technique is robust to gate-dependent errors that arise naturally due to imperfect gate calibration. In particular, our protocol is fully robust against arbitrary gate-dependent errors on the gates that are most difficult to implement, while imperfections in the easier gates introduces an additional error that is essentially proportional to the infidelity.

Our randomized compiling technique requires only a small (classical) overhead in the compilation cost, or, alternatively, can be implemented on the fly with fast classical control. Stochastic Pauli errors with the same average error rate r as a coherent error leads to four major advantages for quantum computation: (i) they have a substantially lower worst-case error rate, (ii) the worst-case error rate can be directly estimated efficiently and robustly via randomized benchmarking experiments, enabling a direct comparison to a threshold estimate to determine if fault-tolerant quantum computation is possible, (iii) the known fault tolerant thresholds for Pauli errors are substantially higher than for coherent errors, and (iv) the average error rate accumulates linearly with the length of a computation for stochastic Pauli errors, whereas it can accumulate quadratically for coherent errors.

Randomizing quantum circuits has been previously proposed. However, these proposals have specific limitations that our technique circumvents. The proposal for inserting Pauli gates before and after Clifford gates is a special case of our technique when the only gates to be implemented are Clifford gates. However, this technique does not account for non-Clifford gates whereas our generalized technique does. As a large number of non-Clifford gates are required to perform useful quantum computations and are often more difficult to perform fault-tolerantly, our generalized technique should be extremely valuable in practice. Moreover, previous proposals assume that the Pauli gates are essentially perfect whereas we prove that our technique is robust to imperfections in the Pauli gates. Additionally, a method called Pauli-Random-Error-Correction (PAREC) has been shown to eliminate static coherent errors. However, PAREC involves changing the multi-qubit gates in each step of the computation. As multi-qubit errors are currently the dominant error source in most experimental platforms and typically depend strongly on the gate to be performed, it is unclear how robust PAREC will be against gate-dependent errors on multi-qubit gates and consequently against realistic noise. By way of contrast, our technique is completely robust against arbitrary gate-dependent errors on multi-qubit gates.

We begin by proposing a standardized form for compiled quantum circuits based on an operational distinction between ‘easy’ and ‘hard’ gates, that is, gates that can be implemented in a given experimental platform with relatively small and large amounts of noise respectively. We also propose a specific choice of ‘easy’ and ‘hard’ gates that is well-suited to many architectures for fault-tolerant quantum computation.

In order to experimentally implement a quantum algorithm, a quantum circuit is compiled into a sequence of elementary gates that can be directly implemented or have been specifically optimized. Typically, these elementary gates can be divided into easy and hard gate sets based either on how many physical qubits they act on or how they are implemented within a fault-tolerant architecture. In near term applications of universal quantum computation without quantum error correction, such as quantum simulation, the physical error model and error rate associated with multi-qubit gates will generally be distinct from, and much worse than, those associated with single qubit gates. In the long-term, fault-tolerant quantum computers will implement some operations either transversally (that is, by applying independent operations to a set of physical qubits) or locally in order to prevent errors from cascading. However, recent ‘no-go’ theorems establish that for any fault-tolerant scheme, there exist some operations that cannot be performed in such a manner and so must be implemented via other means, such as magic-state injection or gauge fixing.

The canonical division that we consider is to set the easy gates to be the group generated by Pauli gates and the phase gate R=|0

0|+i|

1|, and the hard gate set to be the Hardamard gate H, the π/8 gate √{square root over (R)} and the two-qubit controlled-Z gate Δ(Z)=|0

0|⊗I+|0

0|⊗Z. Such circuits are universal for quantum computation and naturally suit many fault-tolerant settings, including CSS codes with a transversal T gate (such as the 15-qubit Reed-Muller code), color codes and the surface code. While some of the ‘hard’ gates may be easier than others in a given implementation, it is beneficial to make the set of easy gates as small as possible since our scheme is completely robust to arbitrary variations in errors over the hard gates.

With such a division of the gates, the target circuit can be reorganized into a circuit (the ‘bare’ circuit) consisting of K clock cycles, where each cycle consists of a round of easy gates followed by a round of hard gates applied to disjoint qubits as in FIG. 3 a. To concisely represent the composite operations performed in individual rounds, we use the notational shorthand {right arrow over (A)}=A₁⊗ . . . ⊗A_(n) and define G_(k) to be the product of all the hard gates applied in the kth cycle. We also set G_(k)=I without loss of generality, so that the circuit begins and ends with a round of easy gates.

We now specify how standardized circuits in the above form can be randomized in order to average errors in the implementations of the elementary gates into an effective stochastic channel, that is, into a channel E that maps any n-qubit state p to

$\begin{matrix} {{ɛ(p)} = {\sum\limits_{P \in P_{d}^{\otimes n}}{c_{P}P_{\rho}P^{\dagger}}}} & (4) \end{matrix}$

where P_(d) ^(⊗n) is the set of d^(2n) generalized Pauli operators and the coefficients c_(p) are a probability distribution over P_(d) ^(⊗n). For qubits (d=2), P₂ is the familiar set of four Hermitian and unitary Pauli operators {I, X, Y, Z}.

Let C denote the group generated by the easy gates and assume that it contains a subset T such that

ε^(T) =

T ^(†) εT   (5)

is a stochastic channel for any channel ε, where

ƒ(x)=|X|⁻¹

ƒ(

) denotes the uniform average over a set X (typically a gate set implicit from the context). The canonical example of such a set is P_(d) ^(⊗n) or any group containing P_(d) ^(⊗n).

We propose the following randomized compiling technique, where the randomization should ideally be performed independently for each run of a given bare circuit. Each round of easy gates {right arrow over (C)}_(k) in the bare circuit of FIG. 3a is replaced with a round of randomized dressed gates

{tilde over (C)} _(k) ={right arrow over (T)} _(k) {right arrow over (C)} _(k) {right arrow over (T)} _(k−1) ^(c)   (6)

as in FIG. 3B, where the T_(j,k) are chosen uniformly at random from the twirling set T and the correction operators are set to {right arrow over (T)}_(k) ^(c)=G_(k){right arrow over (T)}_(k) ^(†)G_(k) ^(†) to undo the randomization from the previous round. The edge terms {right arrow over (T)}₀ ^(c) and {right arrow over (T)}_(k) can either be set to the identity or also randomized depending on the choice of the twirling set and the states and measurements

The dressed gates should then be compiled into and implemented as a single round of elementary gates as in FIG. 3C rather than being implemented as three separate rounds of elementary gates. In order to allow the dressed gates to be compiled into a single easy gate, we require {right arrow over (T)}_(k) ^(c) ∈ C^(⊗n) for all {right arrow over (T)}_(k) ∈ T^(⊗n). The example with T=P_(d) that has been implicitly appealed to and described as “toggling the Pauli frame” previously is a special case of the above technique when the hard gates are Clifford gates (which are defined to be the gates that map Pauli operators to Pauli operators under conjugation), but breaks down when the hard gates include non-Clifford gates such as the π/8 gate. For the canonical division into easy and hard gates from the previous section, we set T=P₂, C to be the group generated by R and P₂ (which is isomorphic to the dihedral group of order 8) and the hard gates to be rounds of H, √{square root over (R)} and Δ(Z) gates. Conjugating a Pauli gate by H or Δ(Z) maps it to another Pauli gate, while conjugating. by √{square root over (R)} maps X^(X)Z^(Z) to R^(X)X^(X)Z^(Z) (up to a global phase). Therefore, the correction gates, and hence the dressed gates, are all elements of the easy gate set.

The tailored noise is not realized in any individual choice of sequences. Rather, it is the average over independent random sequences. However, while each term T^(†)εT in the tailored noise can have a different effect on an input state ρ, if the twirling gates are independently chosen on each run, then the expected noise over multiple runs is exactly the tailored noise. Independently sampling the twirling gates each time the circuit is run introduces some additional overhead, since the dressed gates (which are physically implemented) depend on the twirling gates and so need to be recompiled for each experimental run of a logical circuit. However, this recompilation can be performed in advance efficiently on a classical computer or else applied efficiently ‘on the fly’ with fast classical control. Moreover, this fast classical control is exactly equivalent to the control required in quantum error correction so imposes no additional experimental burden.

We will prove below that our technique tailors noise satisfying various technical assumptions into stochastic Pauli noise. We expect the technique will also tailor more general noise into approximately stochastic noise, though leave a fully general proof as an open problem.

We now prove that our randomized compiling scheme results in an average stochastic noise channel for Markovian noise that depends arbitrarily upon the hard gates but is independent of the easy gate. Under this assumption, the noisy implementations of the kth round of easy gates {right arrow over (C)}_(k) and hard gates {right arrow over (G)}_(k) can be written as ε_(e){right arrow over (C)} and G_(k)ε(G_(k)) respectively, where ε_(e) and ε(G_(k)) are n-qubit channels that can include multi-qubit correlations and ε(*)can depend arbitrarily on the argument, that is, on which hard gates are implemented.

Theorem 1. Randomly sampling the twirling gates {right arrow over (T)}_(k)T independently in each round tailors the noise at each time step (except the last) into stochastic Pauli noise when the noise on the easy gates is gate-independent.

Proof The key observation is that if the noise in rounds of easy gates is some fixed noise channel ε_(e), then the dressed gates in equation (6) have the same noise as the bare gates and so compiling in the extra twirling gates in FIG. 4c does not change the noise at each time step, as illustrated in FIGS. 4A and 4D. Furthermore, the correction gates T_(k,j) ^(c) are chosen so that they are the inverse of the randomizing gates when they are commuted through the hard gates, as illustrated in FIGS. 4B and 4C. Consequently, uniformly averaging over the twirling gates in every cycle reduces the noise in the kth cycle to the tailored noise

_(k)=

_({right arrow over (T)}) {right arrow over (T)} ^(†)ε(G _(k))ε_(e) {right arrow over (T)}  (7)

where for channels

and

,

denotes the channel whose action on a matrix is

(

) (M). When T=P, the above channel is a Pauli channel. Moreover, by the definition of a unitary 1-design, the above sum is independent of the choice of T and so is a Pauli channel for any unitary 1-design.

Theorem 1 establishes that the noise in all but the final cycle can be exactly tailored into stochastic noise (albeit under somewhat idealized conditions which will be relaxed below). To account for noise in the final round, we can write the effect corresponding to a measurement outcome |{right arrow over (z)}

as

(|{right arrow over (z)}

{right arrow over (z)}|) for some fixed noise map

. If P⊂ C we can choose {right arrow over (T)}_(K) uniformly at random from P^(⊗n). A virtual Pauli gate can then be inserted between the noise map

and the idealized measurement effect |{right arrow over (z)}

{right arrow over (z)}| by classically relabeling the measurement outcomes to map {right arrow over (z)}→{right arrow over (z)}⊗{right arrow over (x)}, where ⊗ denotes entry-wise addition modulo two. Averaging over {right arrow over (T)}_(K) with this relabeling reduces the noise in the final round of single-qubit Clifford gates and the measurement to

A =

_({right arrow over (P)}) {right arrow over (P)}

ε _(e) {right arrow over (P)}  (8)

This technique can also be applied to quantum non-demolition measurements on a subset of the qubits (as in, for example, error-correcting circuits), where the unmeasured qubits have randomizing twirling gates applied before and after the measurement.

By theorem 1, our technique is fully robust to the most important form of gate-dependence, namely, gate-dependent errors on the hard gates. However, theorem I still requires that the noise on the easy gates is effectively gate-independent. Because residual control errors in the easy gates will generally produce small gate-dependent (coherent) errors, we will show that the benefits of noise tailoring can still be achieved in this physically realistic setting.

When the noise depends on the easy gates, the tailored noise in the kth cycle from equation (7) becomes

=

_({right arrow over (T)}) ₁ _(, . . . , {right arrow over (T)}) _(k) {right arrow over (T)} _(k) ^(†)ε(G _(k))ε({tilde over ({right arrow over (C)})} _(k)){right arrow over (T)} _(k),   (9)

which depends on the previous twirling gates through {tilde over ({right arrow over (C)})}_(k) by equation 6. This dependence means that we cannot assign independent noise to each cycle of a tailored circuit.

However, in theorem 2 we show that implanting a circuit with gate-dependent noise ε({tilde over ({right arrow over (C)})}_(k)) instead of the corresponding gate-independent noise

$\begin{matrix} {ɛ_{k}^{T} = {_{{\overset{\rightarrow}{\overset{\sim}{C}}}_{k}}{ɛ\left( {\overset{\rightarrow}{\overset{\sim}{C}}}_{k} \right)}}} & (10) \end{matrix}$

introduces a relatively small additional error. We show that the additional error is especially small when T is a group normalized by C, that is, CTC^(†) ∈ T for all C ∈ C, T ∈ T. This condition is satisfied in many practical cases, including the scenario where T is the Pauli group and C is the group generated by Pauli and R gates. The stronger bound reduces the contributions from every cycle by orders of magnitude in parameter regimes of interest (i.e., ∈[ε(G_(k−1)ε_(k−1) ^(T))]≤10⁻², comparable to current experiments), so that the bound on the additional error grows very slowly with the circuit length.

Theorem 2. Let C_(GD) and C_(GI) be tailored circuits with gate-dependent and gate-independent noise on the easy gates irrespectively. Then

$\begin{matrix} \left. ||{_{GD} - _{GI}}||{}_{\Diamond}{\leq {\sum\limits_{ = 1}^{}\; _{{\overset{\rightarrow}{T}}_{1},\ldots,{\overset{\rightarrow}{T}}_{}}}}||{{ɛ\left( {\overset{\rightarrow}{\overset{\sim}{C}}}_{} \right)} - ɛ_{}^{T}}||{}_{\bullet}. \right. & (11) \end{matrix}$

When T is a group normalized by C, this can be improved to

$\begin{matrix} \left. ||{_{GD} - _{GI}}||{}_{\Diamond}{\leq {\sum\limits_{ = 2}^{}{2_{{\overset{\rightarrow}{\overset{\sim}{C}}}_{}}{\quad\left. ||{{ɛ\left( {\overset{\rightarrow}{\overset{\sim}{C}}}_{} \right)} - ɛ_{}^{T}}||{\in {\left\lbrack {{ɛ\left( G_{ - 1} \right)}ɛ_{ - 1}^{T}} \right\rbrack + _{{\overset{\rightarrow}{\overset{\sim}{C}}}_{1}}}}||{{ɛ\left( {\overset{\rightarrow}{\overset{\sim}{C}}}_{1} \right)} - ɛ_{1}^{T}}||{}_{\Diamond}. \right.}}}} \right. & (12) \end{matrix}$

Proof. Let

_(k) =G _(k)ε(G _(k))ε({tilde over ({right arrow over (C)})} _(k)){tilde over ({right arrow over (C)})} _(k)

_(k) =G _(k)ε(G _(k))ε_(k) ^(T) {tilde over ({right arrow over (C)})} _(k),   (13)

where

_(k) and

_(k), implicitly depend on the choice of twirling gates. Then the tailored circuits under gate-dependent and gate-independent noise are

C _(GD)=

_(a)

_(K):1

C _(GI)=

_(a)

_(K):1,   (14)

respectively, where

_(a:b)=

_(a) . . .

_(b) (note that this product is non-commutative) with

_(K:K+1)=

_(0:1)=

and the expectation is over all {right arrow over (T)}_(a) for a=1, . . . . , K. Then by a straightforward induction argument,

$\begin{matrix} {{_{\text{:}1} - \mathcal{B}_{\text{:}1}} = {\sum\limits_{ = 1}^{}\; {{_{{\text{:}} + 1}\left( {_{} - \mathcal{B}_{}} \right)}\mathcal{B}_{ - {1\text{:}1}}}}} & (15) \end{matrix}$

for any choice of the twirling gates. By the triangle inequality,

$\begin{matrix} {\left. ||{_{GD} - _{GI}} \right.||_{\Diamond} = \left. ||{_{a}{\sum\limits_{ = 1}^{}\; {{_{{\text{:}} + 1}\left( {_{} - \mathcal{B}_{}} \right)}\mathcal{B}_{ - {1\text{:}1}}}}}||{}_{\Diamond}{\leq {_{a}{\sum\limits_{ = 1}^{}\; {\quad{\left. ||{{_{{\text{:}} + 1}\left( {_{} - \mathcal{B}_{}} \right)}\mathcal{B}_{ - {1\text{:}1}}}||{}_{\Diamond}{\leq {_{a}\sum\limits_{ = 1}^{}}}\;||{{ɛ\left( {\overset{\rightarrow}{\overset{\sim}{C}}}_{} \right)} - ɛ_{}^{T}} \right.||_{\Diamond},}}}}} \right.} & (16) \end{matrix}$

where the second inequality follows from the submultiplicativity

∥

∥_(⋄)≤∥

∥_(⋄)∥

∥_(⋄)  (17)

of the diamond norm and the normalization ∥

∥_(⋄)=1 which holds for all quantum channels

.

We can substantially improve the above bound by evaluating some of the averages over twirling gates before applying the triangle inequality. In particular, leaving the average over {right arrow over (T)}_(k−1) inside the diamond norm in equation (16) for every term except k=1 gives

$\begin{matrix} {\left. ||{_{GD} - _{GI}}||{}_{\Diamond}{\leq {\sum\limits_{ = 1}^{}\; _{a \neq { - 1}}}}||{_{ - 1}\delta_{}\gamma_{}}||{}_{\Diamond}{+ _{a}}||{{ɛ\left( {\overset{\rightarrow}{\overset{\sim}{C}}}_{1} \right)} - ɛ_{1}^{T}} \right.||_{\Diamond},} & (18) \end{matrix}$

where

δ_(k)=ε(

_(k))−ε_(k) ^(T)

γ_(k=) {tilde over ({right arrow over (C)})} _(k) G _(k−1)ε(G _(k−1))ε_(k−1) ^(T) {right arrow over (T)} _(k−1),   (19)

and δ_(k)γ_(k) is the only factor of

_(K:k+1)(

_(k)−

_(k))

_(k−1:1) that depends on {right arrow over (T)}_(k−1). Substituting ε(G_(k−1))ε_(k−1) ^(T)=(ε(G_(k−1))ε_(k−1) ^(T)−

)+

in γ_(k) gives

$\begin{matrix} {{{_{k - 1}\delta_{k}} = {{_{k - 1}\delta_{k}{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}{G_{k - 1}\left\lbrack {{{\mathcal{E}\left( G_{k - 1} \right)}\mathcal{E}_{k - 1}^{T}} - \mathcal{I}} \right\rbrack}{\overset{\rightarrow}{T}}_{k - 1}} + {_{k - 1}\delta_{k}{\overset{\rightarrow}{T}}_{k}{\overset{\rightarrow}{C}}_{k}G_{k - 1}}}},} & (20) \end{matrix}$

where the only factor in the second term that depends on {right arrow over (T)}_(k−1) is δ_(k). When T is a group normalized by C,

$\begin{matrix} \begin{matrix} {{_{k - 1}\delta_{k}} = {{_{k - 1}{\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)}} - \mathcal{E}_{k}^{T}}} \\ {= {{_{k - 1}{\mathcal{E}\left( {{{\overset{\rightarrow}{C}}_{k}\left\lbrack {{\overset{\rightarrow}{C}}_{k}^{\dagger}{\overset{\rightarrow}{T}}_{k}{\overset{\rightarrow}{C}}_{k}} \right\rbrack}{\overset{\rightarrow}{T}}_{k - 1}^{c}} \right)}} - \mathcal{E}_{k}^{T}}} \\ {{= _{\overset{\rightarrow}{T}}},{{\mathcal{E}\left( {{\overset{\rightarrow}{C}}_{k}{\overset{\rightarrow}{T}}^{\prime}} \right)} - \mathcal{E}_{k}^{T}}} \\ {= 0} \end{matrix} & (21) \end{matrix}$

for any fixed value of {right arrow over (T)}_(k), using the fact that {hg: g ∈ G}=G for an group G and h ∈ G and that

_({right arrow over (T)}) _(†) ε({right arrow over (C)}_(k){right arrow over (T)}^(†)) is independent of {right arrow over (T)}_(k). Therefore

$\begin{matrix} {{{{_{GD} - _{GI}}}_{\Diamond} = {{{_{j}\left( {_{K:1} - \mathcal{B}_{K:1}} \right)}}_{\Diamond} \leq {{\delta_{1}}_{\Diamond} + {\sum\limits_{k = 2}^{K}{_{j \neq {k - 1}}{{_{k - 1}\delta_{k}\gamma_{k}}}_{\Diamond}}}} \leq {{\delta_{1}}_{\Diamond} + {\sum\limits_{k = 2}^{K}{_{j \neq {k - 1}}{{_{{\overset{\rightarrow}{T}}_{k - 1}}\delta_{k}{\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \times {G_{k - 1}\left\lbrack {{{\mathcal{E}\left( G_{k - 1} \right)}\mathcal{E}_{k - 1}^{T}} - \mathcal{I}} \right\rbrack}{\overset{\rightarrow}{T}}_{k - 1}}}_{\Diamond}}}} \leq {{\sum\limits_{k = 2}^{K}{_{j}{\delta_{k}}_{\Diamond}{{{{\mathcal{E}\left( G_{k - 1} \right)}\mathcal{E}_{k - 1}^{T}} - \mathcal{I}}}_{\Diamond}}} + {\delta_{1}}_{\Diamond}}}},} & (22) \end{matrix}$

where we have had to split the sum over k as {right arrow over (T)}_(o) is fixed to the identity.

There are two particularly important scenarios in which the effect of gate-dependent contributions need to be considered and which determine the physically relevant value of K. In near-term applications such as quantum simulators, the following theorem would be applied to the entire circuit, while in long-term applications with quantum error correction, the following theorem would be applied to fragments corresponding to rounds of error correction. Hence under our randomized compiling technique, the noise on the easy gates imposes limit either on the useful length of a circuit without error correction or on the distance between rounds of error correction. It is important to note that a practical limit in K is already imposed, in the absence of our technique, by the simple fact that even Pauli noise accumulates linearly in time, so

${r\left( _{k} \right)}{\operatorname{<<}\frac{1}{K}}$

is already required to ensure that the output of any realistic circuit remains close to the ideal circuit.

While theorem 2 provides a very promising bound, it is unclear how to estimate the quantities

$\frac{1}{2}_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{{{\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} - \mathcal{E}_{k}^{T}}}_{\Diamond}$

without performing full process tomography. To remedy this, we now provide the following bound in terms of the infidelity which can be efficiently estimated via randomized benchmarking. We expect the following bound is not tight as we use the triangle inequality to tarn the deviation from the average noise into deviations from no noise, which should be substantially larger. However, even the following loose bound is sufficient to rigorously guarantee that our technique significantly reduces the worst-case error, as illustrated in FIG. 5 for a two-qubit gate in the bulk of a circuit (i.e., with k>1).

The following bound could also be substantially improved if the noise on the easy gates is known to be close to depolarizing (even if the hard gates have strongly coherent errors), as quantified by the unitary. However, rigorously determining an improved bound would require analyzing the protocol for estimating the unitarily under gate-dependent noise, which is currently an open problem.

Theorem 3. For arbitrary noise

$\begin{matrix} {{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{{{\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} - \mathcal{E}_{k}^{T}}}_{\Diamond}} \leq {{2{\epsilon \left( \mathcal{E}_{k}^{T} \right)}} + {2{\sqrt{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack}^{2}}.}}}} & (23) \end{matrix}$

For n-qubit circuits with local noise on easy gates,

$\begin{matrix} {{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{{{\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} - \mathcal{E}_{k}^{T}}}_{\Diamond}} \leq {\sum\limits_{j = 1}^{n}{4\sqrt{6{r\left\lbrack {{\overset{\_}{ɛ}}_{j}^{T}\left( C_{j,k} \right)} \right\rbrack}}}}} & (24) \end{matrix}$

for k=1, . . . , K, where ε_(j,k) ^(T)=

_({right arrow over (C)}) _(i.k) ε_(j)({tilde over (C)}_(j,k)) is the local noise on the jth qubit averaged over the dressed gates in th kth cycle.

Proof. First note that, by the triangle inequality,

$\begin{matrix} {{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{{{\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} - \mathcal{E}_{k}^{T}}}_{\Diamond}} = {{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{{{\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} - \mathcal{I} + \mathcal{I} - \mathcal{E}_{k}^{T}}}_{\Diamond}} \leq {{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}\;}{{{\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} - \mathcal{I}}}_{\Diamond}} + {{\mathcal{I} - \mathcal{E}_{k}^{T}}}_{\Diamond}} \leq {{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}2{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack}} + {2{{\epsilon \left( \mathcal{E}_{k}^{T} \right)}.}}}}} & (25) \end{matrix}$

By the Cauchy-Schwarz inequality,

$\begin{matrix} {{\left( {_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack}} \right)^{2} = {{\left( {\sum\limits_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{{{\# {\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}}^{- 1}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack}}} \right)^{2} \leq {\left( {\sum\limits_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{{\# {\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}}^{- 2}} \right)\left( {\sum\limits_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack}^{2}} \right)} \leq {{{\# {\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}}^{- 1}\left( {\sum\limits_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack}^{2}} \right)}} = {_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack}^{2}}}},} & (26) \end{matrix}$

where #{tilde over ({right arrow over (C)})}_(k) is the number of different dressed gates in the kth round.

For local noise, that is, noise of the form ε₁ ⊗ . . . ε_(n) where ε_(j) is the noise on the jth qubit,

$\begin{matrix} {{{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack} = {{\frac{1}{2}{{{\overset{n}{\underset{j = 1}{\otimes}}{\mathcal{E}_{j}\left( {{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}_{j,k} \right)}} - \mathcal{I}}}_{\Diamond}} \leq {\sum\limits_{j = 1}^{n}{\frac{1}{2}{{{\mathcal{E}_{j}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k} \right)} - \mathcal{I}}}_{\Diamond}}} \leq {\sum\limits_{j = 1}^{n}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k} \right)} \right\rbrack}}}},} & (27) \end{matrix}$

where we have used the analog of equation (15) for the tensor product and

∥A⊗B∥ _(⋄) ≤∥A∥ _(⋄) ∥B∥ _(⋄),   (28)

which holds for all A and B due to the submultiplicativity of the diamond norm, and the equality ∥A⊗B∥_(⋄)=∥A∥_(⋄). Similarly,

$\begin{matrix} {{\epsilon \left( \mathcal{E}_{k}^{T} \right)} = {\sum\limits_{j = 1}^{n}{\epsilon \left( \mathcal{E}_{j,k}^{T} \right)}}} & (29) \end{matrix}$

where ε_(j,k) ^(T)=

_(T) _(j,k−1) ,T_(j,k)ε({tilde over (C)}_(j,k)). We then have

$\begin{matrix} {{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} \right\rbrack}} \leq {\sum\limits_{j = 1}^{n}{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k} \right)} \right\rbrack}}} \leq {\sum\limits_{j = 1}^{n}\sqrt{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k} \right)} \right\rbrack}^{2}}}} & (30) \end{matrix}$

where the second inequality is due to the Cauchy-Schwarz inequality as in equation (26). Returning to equation (25), we have

$\begin{matrix} {{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{k}}{{{\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{k} \right)} - \mathcal{E}_{k\;}^{T}}}_{\Diamond}} \leq {{\sum\limits_{j = 1}^{n}{2{\epsilon \left( \mathcal{E}_{j,k}^{T} \right)}}} + {2\sqrt{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k}}{\epsilon\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k} \right)} \right\rbrack}^{2}}}} \leq {{\sum\limits_{j = 1}^{n}{2\sqrt{6{r\left( \mathcal{E}_{j,k}^{T} \right)}}}} + {2\sqrt{_{{\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k}}6{r\left\lbrack {\mathcal{E}\left( {\overset{\overset{\rightarrow}{\sim}}{C}}_{j,k} \right)} \right\rbrack}}}} \leq {\sum\limits_{j = 1}^{n}{4\sqrt{6{r\left( \mathcal{E}_{j,k}^{T} \right)}}}}} & (31) \end{matrix}$

for local noise, where the second inequality follows from equation (3) with d=2 and the third from the linearity- of the infidelity.

Tailoring experimental noise into stochastic noise via our technique provides several dramatic advantages, which we now illustrate via numerical simulations. Our simulations are all of six-qubit circuits with the canonical division into easy and hard gates. That is, the easy gates are composed of Pauli gates and the phase gate R=|0

0|+i|1

1|, while the hard gates are the Hardamard, π/8 gate √{square root over (R)} and the two-qubit controlled-Z gate Δ(Z)=|0

0|⊗I+|0

0|⊗Z. Such circuits are universal for quantum computation and naturally suit many fault-tolerant settings, including CSS codes with a transversal T gate (such as the 15-qubit Reed-Muller code), color codes and the surface code.

We quantify the total noise in a noisy implementation C_(noisy) of an ideal circuit C_(id) by the variational distance

$\begin{matrix} {\tau_{noisy} = {\sum\limits_{j}{\frac{1}{2}{{{\Pr \left( j \middle| C_{noisy} \right)} - {\Pr \left( j \middle| C_{id} \right)}}}}}} & (15) \end{matrix}$

between the probability distributions for ideal computational basis measurements after applying C_(noisy) and C_(id) to a system initialized in the |0

^(⊗n) state. We do not maximize over states and measurements, rather, our results indicate the effect of noise under practical choices of preparations and measurements.

For our numerical simulations, we add gate-dependent over rotations to each gate, that is, we perturb one of the eigenvectors of each gate U bye^(iδU). For single-qubit gates, the choice of eigenvector is irrelevant (np to a global phase), while for the two-qubit Δ(Z) gate, we add the phase to the |11

state.

We perform two sets of numerical simulations to illustrate two particular properties. First, FIG. 7 shows that our technique introduces larger relative improvement as the infidelity decreases, that is, approximately a factor of two on a log scale, directly analogous to the

$\frac{r}{\sqrt{r}}$

scaling for the worst case error (although recall that our simulations are for computational basis states and measurements and do not maximize the error over preparations and measurements). For these simulations, we set δ_(U) so that the Δ(Z) gate has an infidelity of r[Δ(Z)] and so that all single-qubit gates have an infidelity of r[Δ(Z)]/10 (regardless of whether they are included in the “easy” or the “hard” set). For the bare circuits (circles), each data point is the variational distance of a randomly-chosen six-qubit circuit with a hundred alternating rounds of easy and hard gates, each sampled uniformly from the sets of all possible. easy and hard gate rounds respectively. For the tailored circuits (squares), each data point is the variational distance between Pr(j|C_(id)) and the probability distribution Pr(j|C_(noisy)) averaged over 10³ randomizations of the bare circuit obtained by replacing the easy gates with (compiled) dressed gates as in equation (6).

Second, FIG. 6 shows that the typical error for both the bare and tailored circuits grows approximately linearly with the length of the circuit. This suggests that, for typical circuits, the primary reason that the total error is reduced by our technique is not because it prevents the worst-case quadratic accumulation of fidelity with the circuit length (although it does achieve this). Rather, the total error is reduced because the contribution from each error location is reduced, where the number of error locations grows linearly with the circuit size. For these simulations, we set δ_(U) so that Δ(Z) gate has an infidelity of 10⁻³ and the easy gates have infidelities of 10⁻⁵. For the bare circuits (blue circles), each data point is the variational distance of a randomly-chosen six-qubit circuit as above with alternating rounds of easy and hard gates, where K varies from five to a hundred. The tailored circuits (red squares) again give the variational distance between the ideal distribution and the probability distribution averaged over 10³ randomizations of the bare circuit.

We have shown that arbitrary Markovian noise processes can be reduced to effective Pauli processes by compiling different sets of uniformly random gates into sequential operations. This randomized compiling technique can reduce the worst case error rate by orders of magnitude and enables threshold estimates for general noise models to be obtained directly from threshold estimates for Pauli noise. Physical implementations can then be evaluated by directly comparing these threshold estimates to the average error rate r estimated via efficient experimental techniques, such as randomized benchmarking, to determine whether the experimental implementation has reached the fault-tolerant regime. More specifically, the average error rate r is that of the tailored channel for the composite noise on a round of easy and hard gates and this can be directly estimated using interleaved randomized benchmarking with the relevant choice of group.

Our technique can be applied directly to gate sets that are universal for quantum computation, including all elements in a large class of fault-tolerant proposals. Moreover, our technique only requires local gates to tailor general noise on multi-qubit gates into Pauli noise. Our numerical simulations in FIG. 6 and FIG. 7 demonstrate that our technique can reduce worst-case errors by orders of magnitude. Furthermore, our scheme should generally produce an even greater effect as fault-tolerant protocols are scaled up, since fault-tolerant protocols are designed to suppress errors, for example, ε→ε^(k) for some scale factor k (e.g., number of levels of concatenation), so any reduction at the physical level is improved exponentially with k. However, while the technique can be directly integrated into fault-tolerant implementations, analyzing the impact on encoded error rates remains an open problem and will generally depend on the specific noise and error-correcting code.

A particularly significant open problem is the robustness of our technique to noise that remains non-Markovian on a time-scale longer than a typical gate time. Non-Markovian noise can be mitigated by techniques such as randomized-dynamic decoupling, which correspond to applying random sequences of Pauli operators to echo out non-Markovian contributions. Due to the random gates compiled in at each time step, we expect that our technique may also suppress non-Markovian noise in a similar manner.

FIG. 5 is a plot 500 showing an upper bound on worst-case errors in simulated executions of an example two-qubit quantum logic gate (e.g., a controlled-not gate) as a function of the infidelity r(ε) of the two-qubit quantum logic gate. The plot 500 in FIG. 5 is shown on a semi-log scale. The plot 500 includes a horizontal axis representing the infidelity r(ε), and the plot 500 includes a vertical axis representing the upper bounds ε^(ab) on the worst case error. The solid line in the plot 500 represents simulations where the bare quantum-logic process is executed without noise-tailoring. The dashed lines in the plot 500 represent simulations where gate-dependent noise is tailored by application of virtual random gates, with simulations for four values (10⁻³, 5×10⁻⁴, 10⁻⁴, 10⁻⁵, as indicated in the plot 500) of the quantity r({right arrow over (e)}_(j,k) ^(T)). For comparison, the chained line in the plot 500 represents simulations where gate-independent noise is tailored by application of virtual random gates.

FIG. 6 is a plot showing errors in simulated executions of an example quantum-logic circuit. The plot 600 includes a horizontal axis representing the number of hard gate rounds, and the plot 600 includes a vertical axis representing the error τ_(noise) computed in a classical-computer simulation of a quantum-logic process executed by an example six-qubit quantum information processor, averaged over 10³ realizations.

The error τ_(noise), shown in the plot 600 is from Equation (32), and is plotted with respect to computational basis measurement outcomes as a function of the average gate error r[Δ(Z)] of the noise on the Δ(Z) gate in six-qubit bare (blue circles) and tailored (red squares) circuits. Each data point in the plot 600 corresponds to an independent random circuit with K cycles, where the (gate dependent) noise on each gate is an over-rotation about the relevant eigenbasis with infidelity 10⁻³ for the A(Z) gates and 10⁻⁵ for all single-qubit gates. The data points for the tailored noise correspond to an average over 10³ independent randomizations of the corresponding bare circuit via Equation (6). As shown in the plot 600, the error rate grows approximately linearly with the number of gate cycles, suggesting that the dominant reason for the error suppression is that the error at each location is suppressed (where there are a linear number of total locations), rather than the suppression of possible quadratic accumulation of coherent errors between locations.

FIG. 7 is a plot 700 showing errors in simulated executions of an example quantum-logic circuit. The plot 700 in FIG. 7 is shown on a semi-log scale. The plot 700 includes a horizontal axis representing the average gate error r[Δ(Z)], and the plot 700 includes a vertical axis representing the error τ^(noise) on a logarithmic scale (log base-10) computed in a classical-computer simulation of a quantum-logic process executed by an example six-qubit quantum information processor, averaged over 10³ independent realizations.

The error τ_(noise) shown in the plot 700 is from Equation (32), and is plotted with respect to computational basis measurement outcomes as a function of the average gate error r[Δ(Z)] of the noise on the Δ(Z) gate in six-qubit bare (blue circles) and tailored (red squares) circuits. Each data point in the plot 700 corresponds to an independent random circuit with 100 cycles, where the (gate dependent) noise on each gate is an over-rotation about the relevant eigenbasis with infidelity r[Δ(Z)] for the Δ(Z) gates and r[Δ(Z)]/10 for all single-qubit gates. The data points for the tailored noise correspond to an average over 10³ independent randomizations of the corresponding bare circuit via Equation (6). As shown in the plot 600, the total error for the bare and tailored circuits differs by a factor of approximately 2 on a log scale, minoring the separation between the worst-case errors for stochastic and unitary channels from Equation (3), although here the error is not maximized over preparations and measurements.

Some of the subject matter and operations described in this specification can be implemented in digital electronic circuitry, or in computer software, firmware, or hardware, including the structures disclosed in this specification and their structural equivalents, or in combinations of one or more of them. Some of the subject matter described in this specification can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage medium for execution by, or to control the operation of, data-processing apparatus. A computer storage medium can be, or can be included in, a computer-readable storage device, a computer-readable storage substrate, a random or serial access memory array or device, or a combination of one or more of them. Moreover, while a computer storage medium is not a propagated signal, a computer storage medium can be a source or destination of computer program instructions encoded in an artificially generated propagated signal. The computer storage medium can also be, or be included in, one or more separate physical components or media (e.g., multiple CDs, disks, or other storage devices).

The term “data-processing apparatus” encompasses all kinds of apparatus, devices, and machines for processing data, including by way of example a programmable processor, a computer, a system. on a chip, or multiple ones, or combinations, of the foregoing. The apparatus can include special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit). The apparatus can also include, in addition to hardware, code that creates an execution environment for the computer program in question, e.g., code that constitutes processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or a combination of one or more of them.

A computer program (also known as a program, software, software application, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages. A computer program may, but. need not, correspond to a file in a file system. A program can be stored in a portion of a file that holds other programs or data (e.g., one or more scripts stored in a markup language document), in a single file dedicated to the program, or in multiple coordinated tiles (e.g., files that store one or more modules, sub-programs, or portions of code). A computer program can be deployed to be executed on one computer or on multiple computers that are located at one site or distributed across multiple sites and interconnected by a communication network.

Some of the processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).

Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random-access memory or both. A computer can include a processor that performs actions in accordance with instructions, and one or more memory devices that store the instructions and data. A computer may also include, or be operatively coupled to receive data from or transfer data to, or both, one or more mass storage devices for storing data, e.g., magnetic disks, magneto optical disks, or optical disks. However, a computer need not have such devices. Devices suitable for storing computer program instructions and data include all forms of non-volatile memory, media and memory devices, including by way of example semiconductor memory devices (e.g., EPROM, EEPROM, flash memory devices, and others), magnetic disks (e.g. internal hard disks, removable disks, and others), magneto optical disks, and CD ROM and DVD-ROM disks. In some cases, the processor and the memory can be supplemented by, or incorporated in, special purpose logic circuitry.

To provide for interaction with a user, operations can be implemented on a computer having a display device (e.g., a monitor, or another type of display device) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse, a trackball, a tablet, a touch sensitive screen, or another type of pointing device) by which the user can provide input to the computer. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback, e.g., visual feedback, auditory feedback, or tactile feedback; and input from the user can be received in any form, including acoustic, speech, or tactile input. In addition, a computer can interact with a user by sending documents to and receiving documents from a device that is used by the user; for example, by sending web pages to a web browser on a user's client device in response to requests received from the web browser.

A computer system may include a single computing device, or multiple computers that operate in proximity or generally remote from each other and typically interact through a communication network. Examples of communication networks include a local area network (“LAN”) and a wide area network (“WAN”), an inter-network (e.g., the Internet), a network comprising a satellite link, and peer-to-peer networks (e.g., ad hoc peer-to-peer networks). A relationship of client and server may arise by virtue of computer programs running on the respective computers and having a client-server relationship to each other.

In a first example, an initial quantum-logic gate sequence is received. A modified quantum-logic gate sequence is generated by applying virtual random gates to the initial quantum-logic gate sequence, such that the initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence. The modified quantum-logic gate sequence can be provided to a quantum information processor for execution.

In a second example, a system includes a quantum information processor and one or more data processors. The data processors are configured to receive an initial quantum-logic gate sequence; generate a modified quantum-logic gate sequence by applying virtual random gates to the initial quantum-logic gate sequence; and providing the modified quantum-logic gate to be executed by the quantum information processor. The initial quantum-logic gate sequence is logically equivalent to the modified quantum-logic gate sequence.

Implementations of the first or second example may include one or more of the following features. The initial quantum-logic gate sequence can include a series of cycles, and the modified quantum-logic gate sequence can be generated by applying virtual random gates in each cycle of the initial quantum-logic gate sequence. After the initial cycle in the series, a portion of the virtual random gates applied in each cycle can be configured to invert one or more of the virtual random gates applied in the preceding cycle. The virtual random gates can include virtual random Pauli gates or dihedral gates. Providing the modified quantum-logic gate to be executed by a quantum information processor can include converting the modified quantum-logic gate into machine code that is executable by the quantum information processor. The virtual random gates can be configured to convert coherent errors in the quantum information processor into stochastic errors in the quantum information processor.

In a third example, a noise-tailoring method includes receiving a bare quantum-logic circuit; generating a set of modified quantum-logic circuits by applying virtual twirling gates and virtual correction gates to the bare quantum-logic circuit; executing the set of modified quantum-logic circuits on a quantum information processor to obtain a set of outcomes; and averaging the set of outcomes to obtain a noise-tailored outcome. The bare quantum-logic circuit is logically equivalent to each of the modified quantum-logic circuits.

Implementations of the third example may include one or more of the following features. The bare quantum-logic circuit can include multiple clock cycles, and the virtual twirling gates and virtual correction gates can be applied to each clock cycle. The virtual random gates can include virtual random Pauli gates or dihedral gates. The virtual twirling gates and virtual correction gates can cause the quantum information processor to execute the modified quantum-logic circuit with a lower worst-case error rate compared to executing the bare quantum-logic circuit on the quantum information processor. The virtual twirling gates and virtual correction gates can cause the quantum information processor to execute the modified quantum-logic circuit with a lower average error rate compared to executing the bare quantum-logic circuit on the quantum information processor.

While this specification contains many details, these should not be construed as limitations on the scope of what may be claimed, but rather as descriptions of features specific to particular examples, certain features that are described in this specification in the context of separate implementations can also be combined. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple embodiments separately or in any suitable subcombination.

A number of embodiments have been described. Nevertheless, it will be understood that various modifications can be made. Accordingly, other embodiments are within the scope of the following claims. 

What is claimed is:
 1. A system comprising: a quantum device comprising a quantum information processor; and one or more data processors configured to perform a method comprising: (A) receiving an initial quantum-logic gate sequence comprising a plurality of gates, wherein the initial quantum-logic gate sequence is organized into a temporal series of cycles including a k−1 cycle and a k cycle, wherein the k−1 cycle temporally precedes the k cycle; (B) for each respective instance in a plurality of instances, executing a procedure comprising: (i) generating a respective modified quantum-logic gate sequence from the initial quantum-logic gate sequence, the respective modified quantum-logic gate comprising (i) a n−1 corresponding cycle representing the k−1 cycle and (ii) an n corresponding cycle representing the k cycle of the initial quantum-logic gate sequence, wherein the n−1 corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a first virtual random gate to a first gate in the k−1 cycle of the initial quantum-logic gate sequence, the n corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a second virtual random gate to a second gate in the k cycle of the initial quantum-logic gate sequence, the first virtual random gate consists of a first random single qubit gate or a combination of the first random single qubit gate and a first correction gate, and the second virtual random gate comprises a combination of (1) a second correction gate that inverts the first random single qubit gate and (2) a second random single qubit gate, and (ii) executing the respective modified quantum-logic gate sequence on the quantum device to obtain a respective outcome; and (C) averaging the respective outcome across the plurality of instances to obtain a noise-tailored outcome for the initial quantum-logic gate sequence.
 2. The system of claim 1, wherein the first cycle includes two or more of the plurality of gates, the second cycle includes two or more of the plurality of gates, and at least one gate in the plurality of gates is a non-Clifford gate.
 3. The system of claim 1, wherein the second correction gate inverts the first random single qubit gate upon commutation through a second gate, wherein the second gate is present in both the n−1 cycle of the respective modified quantum-logic gate sequence and the k−1 cycle of the initial quantum-logic gate sequence.
 4. The system of claim 3, wherein the second gate is a two-qubit gate.
 5. The system of claim 1, wherein the k−1 cycle includes a plurality of single qubit gates, wherein each single qubit gate in the plurality of single qubit gates is applied to a different qubit in the quantum information processor during the first cycle.
 6. The system of claim 1, wherein the n−1 corresponding cycle includes a plurality of single qubit gates, wherein each single qubit gate in the plurality of single qubit gates is applied to a different qubit in the quantum information processor during the first corresponding cycle.
 7. The system of claim 1, wherein the temporal series of cycles further includes a k+1 cycle, wherein the k cycle temporally precedes the k+1 cycle, the respective modified quantum-logic gate sequence further comprises (i) a n+1 corresponding cycle representing the k+1 cycle of the initial quantum-logic gate sequence; the n+1 corresponding cycle of the respective modified quantum-logic gate sequence is formed by applying a third virtual random gate to a third single qubit gate in the k+1 cycle of the initial quantum-logic gate sequence; and the third virtual random gate comprises a combination of (i) a third correction gate that inverts the second random single qubit gate and (ii) a third random single qubit gate.
 8. The system of claim 7, wherein the third correction gate inverts the second random single qubit gate upon commutation through a third gate, wherein the third gate is present in both the n corresponding cycle of the respective modified quantum-logic gate sequence and the k cycle of the initial quantum-logic gate sequence.
 9. The system of claim 8, wherein the third gate is a two-qubit gate.
 10. The system of claim 1, wherein the plurality of instances is at least 1000 instances.
 11. The system of claim 1, wherein the k cycle includes two or more of the plurality of gates; the k−1 cycle includes two or more of the plurality of gates not in the k cycle; the first gate is a first single-qubit gate {right arrow over (C)}_(k) in the k cycle and is replaced by the generating (B)(i) in the respective modified quantum-logic gate sequence with a randomized dressed gate {tilde over (C)}_(k), wherein {tilde over (C)} _(k) ={right arrow over (T)} _(k) {right arrow over (C)} _(k) {right arrow over (T)} _(k−1) ^(c) and wherein {right arrow over (T)}_(k)=is a first correction gate that is randomly selected from a twirling set T of gates, {right arrow over (T)}_(k−1) ^(c)=G_(k−1){right arrow over (T)}_(k−1) ^(†)G_(k−1) ^(†), {right arrow over (T)}_(k−1) ^(†)=an inverse of a second correction gate {right arrow over (T)}_(k−1) that is randomly selected from the twirling set T of gates, wherein {right arrow over (T)}_(k−1) is applied to a second gate {right arrow over (C)}_(k−1) in the k−1 cycle, G_(k−1) is a gate in the k−1 cycle other than {right arrow over (C)}_(k−1) or a product of two or more gates in the k−1 cycle other than {right arrow over (C)}_(k−1), G_(k−1) ^(†) is the inverse of G_(k−1), the first gate {right arrow over (C)}_(k) in the k cycle and the second gate {right arrow over (C)}_(k−1) in the k−1 cycle are members of a set C, the first correction gate {right arrow over (T)}_(k) and the second correction gate {right arrow over (T)}_(k−1) are members of a set T, and the set T is subset of C^(⊗n).
 12. The system of claim 11, wherein the first gate {right arrow over (C)}_(k) in the k cycle is a single-qubit Pauli gate in the set {I, X, Y, Z} or a R =|0

0|+i|1

1|, the second gate {right arrow over (C)}_(k−1) in the k−1 cycle is a single-qubit Pauli gate in the set {I, X, Y, Z} or a R=|0

0|+i|1

1|, G_(k−1) comprises a Hardamard gate H, the π/8 gate √{square root over (R)}, or the two-qubit controlled-Z gate Δ(Z)=|0

0|⊗I+|0

0|⊗Z, and G_(k) comprises a Hardamard gate H, the π/8 gate √{square root over (R)}, or the two-qubit controlled-Z gate Δ(Z)=|0

0|⊗I+|0

0|⊗Z.
 13. The system of claim 11, wherein the first gate {right arrow over (C)}_(k) in the k cycle is a gate that does not exhibit gate dependent error when implemented on the quantum information processor, and the second gate {right arrow over (C)}_(k−1) in the k−1 cycle is a gate that does not exhibit gate dependent error when implemented on the quantum information processor.
 14. The system of claim 11, wherein the first gate {right arrow over (C)}_(k) in the k cycle is a gate that exhibits gate dependent error when implemented on the quantum information processor, and the second gate {right arrow over (C)}_(k−1) in the k−1 cycle is a gate that exhibits gate dependent error when implemented on the quantum information processor.
 15. The system of claim 14, wherein the set T is normalized by the set C such that CTC^(†) ∈ T, wherein C is a first gate in the set C and C^(†) is the logical inverse of the first gate.
 16. The system of claim 11, wherein the randomized dressed gate {tilde over (C)}_(k) is one or more elementary gates directly implemented on the quantum information processor as part of the executing the respective modified quantum-logic gate sequence.
 17. The system of claim 11, wherein G_(k−1) is a product of two or more gates in the k−1 cycle other than {right arrow over (C)}_(k−1).
 18. The system of claim 11, wherein G_(k−1) comprises a two-qubit gate.
 19. The system of claim 1, wherein the first gate in the k−1 cycle of the initial quantum-logic gate sequence is configured to act on one or more qubits of the quantum device.
 20. A method comprising: at a computer system comprising one or more data processors and a memory, the memory comprising non-transitory instructions configured to perform instructions that: (A) receive an initial quantum-logic gate sequence comprising a plurality of gates, wherein the initial quantum-logic gate sequence is organized into a temporal series of cycles including a k−1 cycle and a k cycle, wherein the k−1 cycle temporally precedes the k cycle; (B) for each respective instance in a plurality of instances, execute a procedure comprising: (i) generating a respective modified quantum-logic gate sequence from the initial quantum-logic gate sequence, the respective modified quantum-logic gate comprising (i) a n−1 corresponding cycle representing the k−1 cycle and (ii) a n corresponding cycle representing the k cycle of the initial quantum-logic gate sequence, wherein the n−1 corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a first virtual random gate to a first gate in the k−1 cycle of the initial quantum-logic gate sequence, the n corresponding cycle of the respective modified quantum-logic gate sequence is formed, at least in part, by applying a second virtual random gate to a second gate in the k cycle of the initial quantum-logic gate sequence, the first virtual random gate consists of a first random single qubit gate or a combination of the first random single qubit gate and a first correction gate, and the second virtual random gate comprises a combination of (1) a second correction gate that inverts the first random single qubit gate and (2) a second random single qubit gate, and (ii) executing the respective modified quantum-logic gate sequence on a quantum device to obtain a respective outcome; and (C) average the respective outcome across the plurality of instances to obtain a noise-tailored outcome for the initial quantum-logic gate sequence. 